SystemVerilog Assertions & Functional Coverage FROM SCRATCH
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SystemVerilog Assertions & Functional Coverage FROM SCRATCH
SystemVerilog Assertions and Functional Coverage Languages/Applications FROM SCRATCH. Includes 2005/2009/2012 LRM.
SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional Coverage that covers features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30-year veteran in the design of CPU and SoC who has published the second edition of a book on SVA and FC in 2016 and hold 18 U.S. patents in design verification. The course has 45+ lectures and is 12+ hours in length (with lifetime access) that will take you step by step through learning of the languages.
What you’ll learn
- Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required.
- Make you confident in spotting those critical and hard to find bugs.
- Easily grasp the concepts of multi-threading from a hardware designer perspective
- This course will go step-by-step through each of SystemVerilog Assertions (SVA) language feature and methodology component with practical applications at each step.
- You will also get in-depth knowledge (from scratch) of SystemVerilog Functional Coverage Language, Methodology and Applications.
- Be confident in applying for new jobs or projects knowing that you have in-depth knowledge of two of the most important subjects in Design Verification, namely SVA and FC
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